Semiconductor startup Kepler Computing is preparing to transition its proprietary memory technology into large-scale commercial production, with executive leadership confirming plans to begin manufacturing chips designed to alleviate critical High Bandwidth Memory (HBM) and Static RAM (SRAM) bottlenecks in artificial intelligence hardware by next year. Backed by strategic investors such as Intel Capital, the company is actively forging partnerships across the semiconductor ecosystem to scale its operations and meet surging industry demand.
Founded in 2018 by a team of industry veterans with deep backgrounds in physics, material science, and chip architecture—including three co-founders formerly with Intel—Kepler has quietly built its own specialized fabrication infrastructure. This setup is designed to ramp up its proprietary three-dimensional (3D) and ferroelectric memory technologies. Rather than competing directly with legacy fabrication lines at extreme costs, Kepler’s approach allows a small, specialized Kepler fablet to sit alongside a customer’s traditional legacy fab. According to the company, this setup enables semiconductor manufacturers to leapfrog multiple generations of leading-edge nodes at a fraction of the investment required to build an entirely new advanced node facility.
Crucially, Kepler asserts that its manufacturing methodology bypasses the reliance on extreme ultraviolet (EUV) lithography equipment to reach advanced node performance levels when collaborating with manufacturing partners like GlobalFoundries. This technological departure positions the startup to offer a distinct alternative in a market currently constrained by the immense capital expenditures and tight supply chains associated with cutting-edge lithography.
"We look just like Micron, or SK Hynix, or Samsung," Kepler CEO Debo Olaosebikan told EE Times. "Customers just buy a memory module from us, and then they integrate it with their chip."
The Mounting Pressure on Conventional Memory Architectures
The aggressive scaling of artificial intelligence models has placed unprecedented strain on conventional memory architectures. These stresses manifest across multiple vectors, including soaring design and manufacturing costs for DRAM and HBM, rising energy consumption, challenging heat dissipation requirements, and rapidly diminishing scalability options.
Concurrently, AI data centers are placing severe demands on global energy grids. Industry analyses indicate that a significant majority of the total energy consumed within a modern AI facility is expended not on raw compute, but on routine data fetches moving back and forth between graphics processing units and HBM stacks. As model parameters scale into the trillions, these data transfer bottlenecks create a formidable barrier to efficiency, latency reduction, and sustainable scaling.
Monolithic Stacking and Thermal Management
To overcome these structural limitations, Kepler has focused heavily on advanced integration techniques. Olaosebikan noted that the company has successfully achieved monolithic stacking of devices within a single chip structure while effectively mitigating the thermal challenges that typically plague traditional multi-die configurations.
"That’s why we can avoid EUV," Olaosebikan explained, detailing how the company’s architecture decouples advanced memory density from the requirement to continuously shrink base transistors. "I can take the old big transistor but just use fewer of them and put things on top of that transistor."
Under this paradigm, the foundational transistor layer at the bottom of the stack can be manufactured using established, older nodes utilizing EUV if desired, but without mandating further physical miniaturization of that base layer.
"We’re okay with that," Olaosebikan added, emphasizing that the company aims to amortize the utility of existing transistor nodes by layering novel, high-density devices directly on top.
Kepler CTO Sasi Manipatruni noted that this approach yields tangible density improvements compatible with standard complementary metal-oxide-semiconductor (CMOS) manufacturing flows. "We increase the memory density by a factor of two to three, and it is actually compatible into CMOS," Manipatruni told EE Times.
Manufacturing Readiness and Ecosystem Collaboration
With foundational research and initial prototyping complete, Kepler has reached a critical inflection point in its corporate lifecycle. Srini Ananth, managing director at Intel Capital, noted that the timing aligns perfectly with broader industry needs for non-traditional scaling solutions.
"They already have partners with some of the top leaders in the industry, in the ecosystem, and the time is now for them to take this into larger scale manufacturability," Ananth said. "It opens the door to a new scale of high-performance computing architectures; you’re not constrained any longer by two-dimensional scaling."
Industry observers note that traditional SRAM scaling essentially halted years ago at around the 5-nanometer node, presenting a major roadblock for chip designers attempting to maintain historical performance scaling trends as they move toward more advanced nodes.
"If you can use a backend of line process to get densities that are much higher than what the boundary node supports, you are advancing Moore’s Law," Ananth said. He also highlighted the unique composition of Kepler’s founding team, noting their cross-disciplinary expertise spanning fundamental physics, material science, and advanced chip architecture.
Manipatruni reflected on the company’s origins within Intel’s advanced logic exploration teams. "I was, I think, the first engineer they hired to go find the next transistor," Manipatruni recalled. "Kepler came organically out of that effort when we figured out what is the specific architectural problem and the materials problem that we needed to be addressing. Our architecture addresses the interconnect problem for memory and increases the memory capacity and bandwidth much beyond the HBM roadmap and is not really bound by HBM physics."
Blurring the Lines Between HBM and SRAM
Kepler’s product portfolio centers on two distinct memory technologies designed to blur the traditional boundaries separating high-bandwidth memory from high-speed static memory.
According to Olaosebikan, one of the proprietary memory products serves as a direct replacement for HBM, while the other functions as an advanced SRAM replacement. The company claims these solutions deliver dramatically superior metrics compared to incumbent technologies. Kepler’s memory implementations offer capacities at least ten times larger than conventional SRAM alternatives, alongside a five-to-tenfold increase in bandwidth per watt relative to standard HBM architectures.
While executives are open about the performance metrics and architectural advantages of their designs, they remain tightly guarded regarding the precise material composition of their ferroelectric memory technology.
"We think that if our foreign adversaries know what the material is and know that it allows them to circumvent EUV, they would be all over it," Manipatruni explained. "So, we are being very careful with the materials specifications. Over the past seven years or so, we went through thousands of iterations of discovering the ferroelectric; the composition, the gradients, the electrodes, the whole shebang it takes to discover that class of materials."
To address industry skepticism surrounding the thermal integrity of multi-layer stacking, Kepler co-founder Rajeev Dokania emphasized that the company’s proprietary packaging innovations resolve traditional heating concerns.
"When people do 3D integration, they are worried about thermals," Dokania said. "Our 3D architecture works around that. There’s negligible thermal overhead relative to the traditional way of doing it. That brings in a tremendous amount of bandwidth at a very low energy cost."
Looking ahead, commercial momentum is already building rapidly around the startup’s roadmap. Kepler confirmed that its entire production capacity for the year 2027 has already been fully allocated. While the company has not disclosed the identities of its specific commercial clients and manufacturing partners beyond its public collaboration with GlobalFoundries, executives indicated that their initial wave of customers spans both the AI data center infrastructure and semiconductor manufacturing sectors. Over the longer term, Kepler’s strategic vision extends beyond memory solutions, with future plans to develop proprietary logic chips as the enterprise continues to scale.
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