DRESDEN — GlobalFoundries has officially taken the wraps off its next-generation fully depleted silicon-on-insulator (FD-SOI) technology, unveiling FDX Fusion at its manufacturing hub in Dresden. With this strategic announcement, the semiconductor foundry is placing a major bet that the next explosive phase of the artificial intelligence hardware market will look fundamentally different from the data center-dominated graphics processing unit (GPU) race that has defined the industry in recent years.
The unveiling coincided with a major regional milestone: the topping-off celebration for SPRINT, GlobalFoundries’ ongoing Dresden fab expansion project backed by the European Chips Act. The expansion is actively adding vital cleanroom, laboratory, and high-tech manufacturing capacity at the site, which the company intends to leverage specifically for specialized, highly differentiated semiconductor technologies designed for tomorrow’s intelligent hardware.
According to company leadership, FDX Fusion is engineered from the ground up for machines and autonomous systems that are required to actively sense their environments, make real-time decisions, communicate with other systems, and physically act—moving far beyond pure digital compute. The platform’s inaugural generation is projected to deliver true 7-nm-class digital performance alongside more than twice the transistor density of GlobalFoundries’ original FDX technology platform. Furthermore, it is designed to seamlessly integrate a comprehensive suite of capabilities, including radio frequency (RF), analog and mixed-signal processing, embedded nonvolatile memory, in-memory computing, and dense logic onto a single piece of silicon.
To bring the ambitious architecture to commercial reality, Manfred Horstmann, senior vice president and general manager of European fabs at GlobalFoundries, revealed that the company expects to invest approximately $1 billion over the coming years into FDX Fusion development. This financial commitment includes about $250 million earmarked specifically for the initial capability toolset. Current timelines indicate that demonstrator silicon is targeted for early 2027, with an initial process design kit (PDK) slated to follow by mid-2027.
Speaking in an exclusive interview ahead of the official public announcement, Horstmann explained that the architectural philosophy behind FDX Fusion stems from recognizing a deep division between cloud-based data center requirements and the realities of bringing intelligence to the physical edge.
"Data center AI is extremely power hungry," Horstmann told EE Times. "Physical AI is a different class of problem—and it needs more than compute. It needs sensors, actuators, communications, low power, and cost efficiency."
This operational ethos underpins what GlobalFoundries describes internally with the acronym STAC: sense, think, act, and communicate. Rather than focusing the design strictly on maximizing raw digital compute density, FDX Fusion aims to strike a balance, pairing substantial local processing capabilities with the precise analog, sensing, and interface functions that allow physical machinery to safely and efficiently interact with the surrounding world.
From FD-SOI to FDX Fusion
To understand the engineering leap represented by FDX Fusion, it helps to examine the underlying physics of FD-SOI technology. In GlobalFoundries’ FDX implementation, the transistor channel is constructed within an extremely thin silicon film—measuring approximately 70 angstroms, or 7 nanometers—positioned directly above a buried oxide layer. Because this silicon layer is exceptionally thin, the channel remains inherently fully depleted during operation.
"You don’t have to waste energy depleting the channel," Horstmann noted, highlighting how this configuration grants FDX many of the electrostatic performance advantages typically associated with complex FinFET architectures, but without the manufacturing overhead of actually constructing a physical fin structure. "A lot of the functionality comes from the substrate itself. So we don’t need to build a fin to get a fully depleted transistor."
The development of this advanced strained-silicon substrate is being carried out in close partnership with CEA-Leti and Soitec as part of a collaborative European project identified by Horstmann as "Fast and FAMES." The consortium has successfully established a specialized pilot line in France dedicated to the substrate. Utilizing a strained 70-angstrom silicon film, the design is engineered to boost electron mobility by roughly 25 percent. Horstmann pointed out that this current tripartite collaboration builds directly upon the foundational success of the same consortium that previously partnered with GlobalFoundries to develop the mature 22FDX platform.
This specialized substrate forms a cornerstone of GlobalFoundries’ strategy to achieve 7-nm-class performance metrics while maintaining a significantly simpler manufacturing process flow than what is typically required by advanced FinFET nodes.
"For 7-nm-class performance, we don’t need EUV," Horstmann said, referring to extreme ultraviolet lithography equipment, which remains notoriously expensive and complex to operate.
GlobalFoundries projects that the initial FDX Fusion process will require approximately 50 masks in total. By comparison, Horstmann cited that advanced 2-nm and 3-nm FinFET processes routinely utilize between 70 and 80 masks. "The substrate gives us a much simpler process," he explained, emphasizing that fewer mask layers inherently reduce process complexity, shorten manufacturing cycle times, and minimize the number of potential points of failure, thereby directly supporting higher production yields and lower overall costs.
Instead of relying heavily on EUV lithography, GlobalFoundries plans to utilize advanced ArF immersion lithography systems, supported by tighter overlay control and exceptionally high-precision photomasks sourced from Dresden-based mask manufacturer AMTC. According to Horstmann, ASML’s newest immersion lithography systems deliver substantial improvements in overlay and critical-dimension control, while multi-electron-beam-written masks from AMTC provide roughly 30 percent better overlay and critical-dimension margins compared to standard industry masks.
Physical AI Needs More Than Logic
This deliberate process strategy is critical because GlobalFoundries is not positioning FDX Fusion merely as an incremental, lower-cost alternative path toward smaller digital transistors. Instead, the platform is intentionally optimized to co-locate dense logic alongside the diverse mix of analog, radio frequency, specialized memory, and robust power management functions that physical AI architectures demand.
"You can use the bulk area for high-voltage devices, and the FD-SOI area for dense logic," Horstmann said. "That makes integrating these different functions much simpler."
The company details that FDX Fusion will successfully combine dense digital logic with high-performance RF capabilities, analog and mixed-signal circuitry, ultra-low-leakage operational modes, embedded nonvolatile memory, and emerging in-memory computing architectures. Company specifications indicate the platform is targeted to achieve logic densities ranging from roughly 14 million to 18 million gates per square millimeter, all while preserving the renowned low-power profile and exceptional integration characteristics established by the legacy FDX architecture.
"You maintain the advantages of 22FDX—extremely low power and very good integration with sensors and actuators," Horstmann observed. "Extremely low power is what you need for mobile autonomous systems and drones."
A Different AI Opportunity for Europe
For the European semiconductor landscape, the rise of physical AI addresses an uncomfortable economic reality. Much of the massive infrastructure and ecosystem supporting data center-scale AI is already deeply entrenched in other parts of the world.
"The data center AI train has left the station," Horstmann said. "लेकिन for physical AI, the world is still open."
His core argument is that Europe does not need to duplicate efforts to win a race it missed; rather, physical AI inherently rewards a technological convergence of low-power computing, environmental sensing, resilient communications, analog circuitry, and advanced power electronics. This unique matrix aligns far more closely with Europe’s established, long-standing industrial strengths in semiconductors and embedded systems.
The region surrounding Dresden serves as a vital anchor for this strategic vision. The local microelectronics cluster already plays host to major industry players including GlobalFoundries, Infineon, and Bosch, alongside specialized research organizations, a robust network of equipment and material suppliers, and the incoming European Semiconductor Manufacturing Company (ESMC) joint venture spearheaded by TSMC.
"The cluster is becoming self-propelling," Horstmann said. As the regional ecosystem continues to scale and expand, more specialized suppliers establish local operational capacity, international equipment vendors maintain dedicated service engineering teams nearby, and innovative design houses are naturally drawn to the geographic hub.
Even the establishment of ESMC in the same region—despite representing a commercial competitor—acts as a net positive for the ecosystem, Horstmann pointed out. By expanding Dresden’s overall industrial scale, the presence of multiple major manufacturers makes the entire region substantially more attractive to the global supply chain.
For GlobalFoundries and the broader European technology sector, that unique intersection of heavy manufacturing scale, collaborative research, and highly differentiated process technology creates a distinct window of opportunity.
"Это is a big opportunity for Europe to define a new market," Horstmann concluded, "and to be first."
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