HSINCHU, Taiwan — Global Unichip Corp. (GUC), recognized widely as a leading advanced ASIC provider, has officially announced that its cutting-edge HBM4E PHY and Controller IP is fully design-ready and has already achieved vital adoption among early customer AI ASICs. Manufactured on TSMC’s advanced N2P process node, the newly minted HBM4E physical layer has successfully completed its initial tape-out utilizing TSMC’s state-of-the-art CoWoS-L advanced packaging technology, marking a significant milestone for high-performance computing and artificial intelligence infrastructure.
This latest breakthrough builds directly upon GUC’s previously established, silicon-proven 12 Gbps HBM4 IP portfolio, which was successfully implemented on TSMC’s N3P process. By pushing the boundaries further, the new HBM4E IP successfully elevates data transfer speeds to an impressive 16 Gbps across all validated operating conditions. Crucially, this performance leap is achieved while simultaneously delivering industry-leading power efficiency and an ultra-compact area footprint, two critical metrics for modern artificial intelligence accelerators facing severe thermal and spatial constraints within data center environments.
To guarantee optimal electrical performance, GUC leveraged its proprietary interposer layout technology. This custom approach ensures that the IP is thoroughly optimized for both signal integrity and power integrity across a wide variety of TSMC CoWoS packaging configurations. As modern AI accelerators grow increasingly dense and complex, maintaining rigorous signal and power standards is essential for preventing bottlenecks, reducing latency, and sustaining peak computational throughput during massive parallel processing workloads.
Powering Next-Generation 3D SoIC Architectures
Beyond standard 2.5D integration, the evolution of high-performance computing demands sophisticated 3D stacking solutions. To directly support advanced 3D SoIC architectures, GUC has engineered a specialized face-up variant of its HBM4E IP. This specific configuration is meticulously designed to function as a bottom die within TSMC’s SoIC-X technology ecosystem.
By integrating dedicated Through-Silicon Vias—commonly known as TSVs—for both signal pull-out and feedthrough power delivery to top-tier dies, the architecture establishes a remarkably seamless and efficient pathway for complex 3D integration. This innovative structural design allows chip designers to stack logic and memory vertically with minimal performance degradation, effectively unlocking unprecedented levels of integration density for upcoming generations of artificial intelligence application-specific integrated circuits.
Ensuring Reliability with Advanced Interconnect Monitoring
As chip architectures scale in complexity, ensuring long-term reliability and maintaining rigorous testing standards during production become increasingly challenging. Aligning with GUC’s well-established HBM, GLink, and UCIe product portfolios, the newly introduced HBM4E IP integrates advanced interconnect monitoring technology from proteanTecs.
The inclusion of this sophisticated monitoring solution significantly enhances visibility during the critical PHY testing and characterization phases. Furthermore, it plays a vital role in maximizing in-field performance and overall system reliability throughout the operational lifecycle of the semiconductor device. By providing deep telemetry data from within the silicon itself, developers can better diagnose potential weaknesses, optimize real-time performance, and safeguard mission-critical AI workloads against unexpected hardware failures.
Industry Perspectives on the 2nm HBM4E Milestone
Commenting on the technical significance of the new launch, Igor Elkanovich, Chief Technology Officer of GUC, emphasized the transformative impact the technology will have on the broader artificial intelligence hardware landscape.
"HBM4E marks a major leap forward in bandwidth and system-level performance for next-generation AI accelerators," said Elkanovich. "Reaching 16 Gbps on TSMC’s N2P process underscores GUC’s ability to quickly turn leading-edge process and packaging technology into production-ready HBM solutions."
Elkanovich further highlighted how the new intellectual property fits into the company’s broader technological ecosystem, noting the synergy between various proprietary solutions designed to simplify complex multi-die integrations.
"By uniting our face-up HBM, face-up UCIe, and GLink-3D IPs, GUC delivers a complete interface IP portfolio for 3D SoIC architectures—the foundation for modern AI ASICs—enabling customers to seamlessly connect HBM, chiplets, and 3D dies that leverage the most advanced process technology," Elkanovich added.
For organizations interested in exploring GUC’s comprehensive UCIe IP portfolio and total system solutions utilizing TSMC’s CoWoS and SoIC advanced manufacturing technologies, inquiries can be directed to authorized GUC sales representatives through the company’s official corporate communications channels.
About GUC
Global Unichip Corp. (GUC) operates as a premier advanced ASIC leader, providing the global semiconductor industry with comprehensive IC implementation and SoC manufacturing services. Specializing in cutting-edge process and packaging technologies, the company has established a strong international reputation with corporate presence spanning across China, Europe, Japan, Korea, and North America. Headquartered in Hsinchu, Taiwan, GUC is publicly traded on the Taiwan Stock Exchange under the ticker symbol 3443.
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