SANTA CLARA, Calif. — Expanding its footprint in the artificial intelligence infrastructure landscape, startup Delos Data has announced a significant evolution in its product portfolio by moving into custom silicon. Revealed at the AI Infra Summit, the latest announcements build upon the company’s previously established data center orchestration software, Mosaic, and its high-density server architecture, Asterion, designed for massive scale-up domains. The newest addition to the Delos ecosystem is Apollo, a specialized data interface chiplet aimed at tackling the complex bottlenecks of modern AI workloads.
Apollo is designed to bridge the gap between diverse computing elements within a data center, offering ultra-low latency, guaranteed bandwidth, and advanced resilience. The chiplet is being rolled out in three distinct form factors to address varying integration needs across the industry. These include a 30+ Tbps I/O chiplet designed to sit directly next to an accelerator or XPU, a 10+ Tbps near-packaged optical interface, and a 400+ Gbps card tailored for traditional CPUs and memory endpoints.
By handling critical tasks such as load balancing, network topology management, and failure handling directly at the endpoint, Apollo relieves the host processor of these complex overhead burdens. Delos is targeting order-of-magnitude improvements in speed, resilience, and operational scale compared to what conventional endpoints can achieve on their own. Alongside the silicon rollout, the company confirmed that it has successfully raised more than $100 million in venture capital to fuel its ongoing development and market expansion.
Bridging Heterogeneous Hardware Domains
As artificial intelligence systems grow increasingly complex, the underlying infrastructure must adapt to cater to regular inference, agentic AI, or a combination of both. According to Delos Data CTO Dan Daly, the primary theme emerging in modern infrastructure buildouts is a sophisticated mixture of hardware that demands better integration.
While traditional CPU advocates frequently emphasize the enduring relevance of processors, Daly points out that standard scale-up and scale-out network fabrics traditionally connect only GPUs. Modern AI pipelines, however, require a cohesive domain that seamlessly incorporates GPUs, specialized accelerators, CPUs, memory, and storage. Delos aims to provide a unified data interface that bridges these diverse device types, each operating with its own distinct semantics, and places them into a single, flat, low-latency domain.
This hardware heterogeneity is particularly evident in modern architectures such as prefill-decode disaggregation, where GPUs and dataflow accelerators utilize fundamentally different approaches to memory management. GPUs typically place data within High Bandwidth Memory (HBM), allowing all compute units to access information through a unified memory map centered on data objects and explicit addresses. In contrast, dataflow architectures rely on a continuous stream of data passing through a sequence of operations, where physical location and timing determine how the data is processed. Bridging these distinct semantic models requires advanced interconnect solutions that go beyond traditional switching methods.
Communication semantics present similar hurdles across a cluster. For instance, a CPU and a memory controller may not inherently speak the same language. While traditional data centers rely on switches to facilitate this communication, doing so often incurs unacceptable latency penalties. Delos argues that interconnects must be deeply aware of the semantics of both endpoints to maximize efficiency, serving as the foundational design principle behind the Apollo chiplet.
Reimagining Network Switches and Resilience
Rather than attempting to replace standard network switches, Delos seeks to enhance their utility. By deploying the Apollo chiplet at each individual endpoint, the company aims to enable operators to reuse existing switches of any kind with significantly higher efficiency. This approach opens up the flexibility required for modern inference platforms, which frequently utilize a combination of copper and optical links, varied switch types, and complex topologies that demand rigorous co-design and customization.
Daly emphasizes that this strategy allows operators to extract maximum value from their switching infrastructure—optimizing metrics like radix, latency, low power consumption, and media flexibility—while stripping away legacy cloud or scale-out constraints that no longer serve modern AI workloads. Furthermore, the architecture opens the door to simplifying the physical network between devices, paving the way for more widespread adoption of optical interconnects.
Resiliency across multiple network hops and diverse semantic bridges represents another critical engineering challenge. Many of the computing devices deployed in modern AI clusters were originally designed for traditional board-level environments where memory and Flash access can reliably assume flawless execution. In those legacy settings, read and write operations virtually always succeed.
In large-scale distributed AI environments, however, hardware faults and switch failures are inevitable statistical realities. Delos has engineered Apollo to build in the foundational assumption that operations must remain resilient, ensuring that systems continue to function seamlessly even in the event of a switch failure.
Roadmap, Software Ecosystem, and Deployment
Because the demanding performance requirements of modern AI clusters necessitate the absolute lowest possible latency, Delos determined that its data interface had to be realized directly in silicon. The Apollo chiplet is designed to replace conventional I/O silicon packages adjacent to multi-die GPUs and XPUs, or function as a packaged chip in near-packaged and co-packaged optics environments.
Recognizing that different components within a data center have varied requirements, Delos is also offering a traditional NIC-like form factor. Company CEO Ed Doe noted that this card can temporarily help bridge endpoints—particularly standard CPUs that may not require massive bandwidth but can still benefit significantly from latency improvements—into an existing cluster without necessitating immediate integration of the Apollo chiplet.
The common attributes across all three form factors remain uncompromising latency, enhanced resilience, and the ultimate capability to bring massive scaling elements into a single cohesive domain. Delos currently offers an FPGA-based version of the card for evaluation, with near-packaged optics chips scheduled to appear next year. While the chiplet version shares a tape-out with the NPO variant, extended XPU design cycles mean that the chiplet will not appear in commercial XPU products for another couple of years.
To support customers through the complex process of designing and deploying these interconnected systems, Delos has combined its hardware and software into a unified reference architecture named MoXI, representing a mixture of interconnects spanning hardware, models, switches, links, and topologies. The company also offers Morpheus, a development platform designed to bridge customers’ pre-silicon and lab environments. This platform allows developers to co-design system topologies based on specific workloads and evaluate the performance impact of connectivity changes before committing to physical hardware manufacturing.
Target customers for the Apollo chiplet include major AI chip companies, hyperscale cloud providers, and frontier AI research laboratories developing custom silicon solutions. Meanwhile, Delos’s Mosaic cluster management software is already active in production environments, operating on top of customers’ existing infrastructure. The company’s newly announced server architecture, Asterion, is scheduled to begin sampling at the end of the fourth quarter, while the Morpheus development platform is currently available to users.
Leave a Reply