Memory and storage giant SK hynix has detailed comprehensive plans to reduce its reliance on power-hungry general-purpose CPU cores by developing an in-house specialized core known as the Hynix Transaction Processing Unit, or H-TPU.
Unveiled as part of a strategic shift to address the mounting hardware constraints of modern enterprise storage, the H-TPU is distinct from traditional AI accelerators. Rather than handling heavy machine learning workloads, the H-TPU is designed to offload the repetitive, routine data-handling tasks typically managed by solid-state drive (SSD) controllers. As modern storage drives continue to experience exponential increases in speed, traditional controller designs have been forced to incorporate an ever-increasing number of CPU cores to keep up with the data flow, creating severe efficiency challenges regarding both physical space and energy consumption.
The introduction of the H-TPU addresses these bottlenecks by deploying tiny, specialized processing units arranged in dedicated clusters. These clusters are engineered to handle routine input and output operations using a streamlined, four-stage, in-order pipeline. Meanwhile, high-level management and complex control duties remain under the purview of the traditional Arm-based CPU architecture already standard in modern controllers.
According to details shared by the company, these miniature processing cores boast a remarkably diminutive physical footprint and exceptional energy efficiency. SK hynix claims that an individual H-TPU core consumes only about 2.5 percent of the power demanded by a standard general-purpose CPU core, while occupying a mere 4 percent of its silicon area. Building on these promising architectural advantages, the company now plans to integrate the H-TPU across its broad portfolio of NAND flash and storage products, as reported by industry publication TheElec.
The strategic rationale behind this hardware pivot was outlined in detail by Koo In-jae, SK hynix’s Vice President of system-on-chip (SoC) design. Speaking earlier this week at ISOCC 2026, the International SoC Design Conference, Koo delivered a presentation titled "From SSD Controllers to AI Memory SoCs." During his address, the executive explained that contemporary SSD controller CPUs are rapidly reaching their absolute limits in terms of power dissipation and physical silicon area.
Koo pointed out a fundamental scaling mismatch in the modern storage industry: while PCIe interface bandwidth continues to double with every successive hardware generation, the clock speeds and overall control capabilities of traditional controller CPUs simply cannot keep pace with that relentless upward trajectory. To bridge this growing performance gap, SK hynix reportedly intends to deploy the H-TPU across its entire ecosystem of NAND-based products, with a primary focus on next-generation enterprise SSD controllers.
This architectural intervention comes at a critical juncture for the data center and enterprise computing sectors. The storage industry is currently locked in an unending chase for higher input/output operations per second, commonly known as IOPS, driven largely by the insatiable data demands of modern artificial intelligence infrastructure. As major industry players and hyperscale cloud providers push toward unprecedented performance targets—such as enterprise drives aiming for tens of millions of IOPS to feed AI clusters—the traditional approach of throwing more general-purpose CPU cores at the controller bottleneck has become unsustainable. By shifting repetitive I/O burdens onto hyper-efficient, application-specific structures like the H-TPU, SK hynix aims to sustain future performance scaling without running into the severe thermal and power walls that currently threaten to constrain the evolution of high-speed enterprise storage.
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